Optical, precision engineering cover | chip surface imperfections, target detection

With the rapid development of integrated circuit manufacturing technology, the package size is getting smaller and smaller in wafer-level packaging, and the requirement of defect detection resolution has been raised from micron level to submicron level. The research on submicron level two-dimensional and three-dimensional defect detection and complex defect identification and classification methods can provide key technical support for the research and development of semiconductor chip packaging defect visual detection system with independent intellectual property rights, and thus lay a technical foundation for solving the "bottleneck problem" faced by the semiconductor packaging industry and improving the yield of devices.